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ELEC4602Microelectronics
创建日期：2024-11-06 14:18:54
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Lab 4: Combinational logic design

The objective of this laboratory session is to work with a somewhat larger combinational digital circuit, namely a full-adder, and to design and characterise this adder. For the hand-calculations, you should use the parameters for the NSCU FreePDK 45nm CMOS process published at the course web-site. The hand-calculations should not be carried out in the laboratory session!

Full-adder design

The full-adder symbol and logic function is shown in figure 1.  An example (from Baker) of a static CMOS implementation of the full-adder is shown in figure 2; you may use this schematic or use your own.  The schematic in figure 2 directly implements the logic function in figure 1: the node CO in the first schematic, for instance, is either pulled to VDD through a series of PMOS transistors, or pulled to ground via a series of NMOS transistors.  Looking at the NMOS pull- down network, we can see that CO  is pulled to ground if A and B are both high (causing both bottom-left NMOS transistors to conduct) or CI  is high and either A or B is high; looking at the PMOS pull-up network, we can see that CO is pulled to VDD if A or B islow and CI is low or both A and B are low; thus the logic function is realised.  You should create a cell that contains the schematic of your chosen full-adder, and use test-benches as appropriate for for the simulations that you are going to carry out.

Figure 1: Full-adder symbol (a), known parameters and functions (b)

Transistor types: In this lab, regular thin-oxide transistors (N VTG and P VTG) are used for all transistors.

Figure 2: Static CMOS example implementation of full-adder

Transistor dimensions: As noted in the figure, all transistor dimensions should have a lengths of L = 0.05 µm; you need to choose the widths for all the transistors:  if there is no particular load requirement to a logic gate, the transistors should be chosen as small as possible; while the smallest allowed transistor width is 90 nm, it is most convenient from a layout point of view to choose transistor widths as an integer multiplum of theminmum contact pitch (i.e. WunitN  = 65 nm + 75 nm = 140 nm), so choose this as the unit width for NMOS transistors.  The PMOS transistor unit width is usually chosen one to three times the NMOS transistor one.  The unit widths are the dimensions used in a unit size (or “normal”) inverter.  For more complex gates, like the ones shown in figure 2, transistors are normally increased in width when they appear in series, in order for the delay through the gate to be similar to that of the unit inverter. The normal sizing approach is this: if a transistorsit in a branch with N series transistors between the output and the relevant power supply (ground for NMOS and VDD  for PMOS), the transistor width is chosen as NWunit.

Test set-up: The power supply used in this session is VDD  = 0.9 V; this also means that digital values are either 0 V (0) or 0.9 V (1). In your test-bench, use load capacitances at both full-adder outputs (S and CO) of CL  = 8 fF. Rise and fall times of about 50 ps and data rates about 109 s-1 are probably appropriate.

Verifying logic function

To verify the logic function of your full-adder, apply input voltage waveforms that cycle through all eight input combinations (for instance using vpulse voltage sources with different periods – e.g. 3 ns, 6 ns and 12 ns – at the three inputs and running a transient simulation; see figure 3) and check the outputs to see that the logic function implemented is the desired one.

Finding propagation delays

If the three inputs waveforms are arranged such that they never change state at the same time (as suggested in figure 3), you should be able to find relevant propagation delays in your simulation.

Figure 3: Suggested input waveforms for full-adder

The Delay  time property in the vpulse voltage source is useful for this: arrange your inputs to be delayed, say, 0 ns, 0.5 ns and 1.0 ns. Now, making sure that a change in CI  causes a change in CO, find the H→ L and L→ H CI  to CO propagation delays.

Finding power dissipation

The power dissipation in static CMOS logic is almost exclusively dynamic; i.e. caused by charg- ing parasitic capacitances, and to some extend crow-bar currents. The power dissipation is equal to the power being delivered by VDD  (be sure to have only one VDD  voltage source in your schematic; the one living in your test bench):

where the integral finds the average current delivered by VDD .  Now, find the power dissipa-

tion in your full-adder: in the transient simulation above, plot the current in the power supply

VDD  (probably called  /V1/MINUS or something similar).  To find the time integral of this cur-

rent, in the graph window, select Tools-Calculator which will open up a graph Calculator window. In this, clear the “buffer” entry field by clicking on the Clear  buffer button (or just

use backspace); then, in the graph window click on the supply current name (/V1/MINUS); that

should enter this waveform. in the calculator (probably looking something like IT("/V1/MINUS/")). Now click on iinteg (indefinite integral) in the Special Functions fieldof the Calculator (or just

edit the buffer to read iinteg(IT("/V1/MINUS"))), and click on the Evaluate  the  buffer button (you can choose to have the trace appearing in a New Window if you so choose); this should plot the time integral of your supply current in the graph window. In the graph window, choose Marker-Create Marker  . . . and click OK in the marker creation window.  Repeat this step to create another marker.  Now select both markers and choose Marker-Create  Delta Marker. Move one marker to the start of your time integral signal and the other to the end – the delta marker should now read the average slope of your time integral, and hence the average supply current from which you can calculate the power dissipation.

Corner simulations

The simulations done so far has been carried out using a typical set of process parameters.  In reality, there is a lot of variation between different wafers fabricated.  For digital circuits, it is usually regarded as sufficient to simulate in two worst-case corners (in addition to the typical parameter values), namely the slow corner (low gain, high capacitance) and the fast corner (high gain, low capacitance). To simulate your circuit in the slow corner, in the Virtuoso ADE Explorer window maestro menu choose Setup-Model  Libraries . . ., in the Model Library Setup win- dow, replace the model library that you are using to the on ending in  . . ./hspice_ss.include (as opposed to  . . ./hspice_stat.include), and click OK. Simulations done now are carried out in the slow corner for the process.  Use the same approach carry out simulations in the fast corner (replace model library with the one ending in . . ./hspice_ff.include). Find the H→ L and L→ H CI to CO propagation delays in the slow and the fast corner.

Driving a large load

When driving a large capacitive load from a unit sized gate, it is necessary to inserts buffer in- verters with increasing drive strength (i.e. transistor widths): The NMOS transistor in an inverter of drive strength S has a width of SWunitN  while the PMOS transistor has a width of SWunitP . The usual approach is shown in figure 4 where two inverters are inserted after the unit inverter such that the load capacitance CX  can be driven to the digital value X in reasonable time.  The scale factor k (drive strength ratio between consecutive inverters) is normally in the range 3 to 6.

Change the load capacitance CLS at the S output to 150 fF, and insert suitable buffer inverters, such that this load can be driven at the data rate you have been using in the other simulations; verify this by a transient simulation.

Figure 4: Unit inverter driving large load; inverters are labelled with drive strengths

Report

A short report in  .pdf format on the laboratory exercise must be prepared and uploaded on the course Moodle site no later than the due date. This need to include:

• The schematic of your test bench.

• The schematic of full-adder (explain choice of transistor widths).

• Proof that S is always pulled to ground or VVDD  (but never both).

• Transient simulations showing logic function.

• Transient simulations showing the CI  to CO  propagation delays in the fast and the slow corner (compare this with simple hand calculations using the typical parameters).

• Simulations used for power dissipation calculation, and a calculation of the power dissipa- tion.

• The schematic of the buffer inverters for driving a large load on S.

• Transient simulations showing proper operation when driving a large load on S.

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MAS316/414 ACCT2522 MSIN0181 ATMS 201 COMP3425 MATH7861 SOLA2060 MA 325 7CCEMCTH ECON 432 INFT2051 SOLA 2060 ECOS2002 Stats141XP BIOA02H3 S2022 MA4601 K5 COMP5329 EG 284 IB3A70 WECO1020 COMP3027 Energy ACS61011 MAST20026 STAT 533 MATA31 ENVS257 BEM2031 EC 486 COMP0172 CS3214 EECE5644 IB2B20 COSC2536 COSC1147 COMP6214 5CCM242A COMP0130 AMME2000 MTMG50: EG238 ACF6006 QBUS2810 COSC2391 ECON7560 MATH377 STA305 CS 486 COMP1117B EL648 ELEC3909 ECON 241 COMP 4901W BUSI4428 ENEN20002 ENGN4524 ELEC3115 CSC 413 PSYC 100B ECON1002 MATH256 ANSC20005 MTHS2008 MATH40082 COSC 2406 FIT3174 STA 238 CMT202 Differential Equations MTHM017 GARCH 101 MATH2069 CSC336S ACSC12 ETF2121 CEME 2001 DB B474F ARHT1001 EECS 3311 3220 STATS 786 CS 484 COMP20008 MATH4091 ECE 455 CSCI 204 BUS B200F BA 875 BU5562 COSC 1147 X11 GEOG 101 IMM250F CSE 584A MATH38172 LAB 4 ELEC5882M FINS5523 EE 430 COMP 465 6CCS3PRE 7CCSMNSE FINANCE ACMB02H3 ENGG2112 ELEC5616 SCM B371 CHEM3120 CS22 ECMT2130 MAST30011 ADSPBF706 CENG0013 ACCOUNTING BUSS1040 CHEM 181 MAT136H1 GY 6183 COMP3170 AGRI90089 PHYSICS 1002 ECON10003 IEOR E4004 ACS61012 MATH 40550 MKTG2113 TELE4653 ENSC1004 ECE 232E MK726 MTRX2700 SHEET 3 CSCA08 COMP30027 Math 2XX3 statistic MMAN3200 BISM7213 ECMM109 ECON 2022 FNCE 20005 GR5067 CSCB09 ME 3017 CS 5100 PHYS 2903 COMS 4771 COMP222 COMP 1046 CSC148H1 ISYS2038 FINS2615 OT5206 COMP2048 A6 MECH5770M MA826/20 CMPT 726 STA457 INFS6071 INFS588 integral ECON 216 IRDR 0017 MA323 PA 15213 PSYC2001 ENV222 Statistics ACCT5930 ACCT12 LAND2121 ME 5405 COMM1180 TELE3113 A7 ECE 568 ACCT2019 INFS1200 ENGG1340 CS 1400 ASST3 FINM7409 SWEN30006 INFO2222 FIN20150 SOSS1000 CSSE7231 FINS5513 COMS3200 CECN 702 ECON4060H MN3515 HW2 PSYA02H3 ECON 2112 COMP90051 CS 1652 MA30059 AF1605 MKTG7501 ECO-6003B COM4521 CTM ECON3350 COMP 3804 ELEC9762 BISM 7255 ST22 MATH20014 MNE3122 COMP343 MATH5165 ELE7029 ENGR30002 SEEM3500 ECON7350 RISK5002 FINM7405 COMP90059 MOS 3320B STAT 431 BISM7221 MATH3014 MTH783P EBA 35302 ACS133 BUS2206 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