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Implement the Controller
n Impelment the Single-cycle Processor using
p Datapath components implemented in Lab4
– You need to load your Lab4 circ file as a library for using them
p Controller implemented in this Lab
n Test your implementations using
p TestController
p TestRV32I
3Implement the Controller
n Instructions to support
p Instructions covered in class,
p ECALL instruction
– We use it in a simple way: once the processor encounters an
ECALL instruction, it sets the Halt signal to 1, and the processor
should stop execution (i.e., PC should not be updated any more,
making the processor halts at the ECALL instruction forever)
n You need to implement totally xxx instructions
p See the next slide for more details...
45
You need to
Implement 30
instructions that
are not crossed
out in the table
U-Type
J-Type
I-Type
B-Type
I-Type
S-Type
I-Type
R-TypeTest Your Controller
n A tester named TestController has been provided to
faciliate your testing of your controller locally
p You can upload and test your implementation on EduCoder
after passing the local test, this will reduce your effort
n The tester is almost done
p Test vectors for the 30 instructions, as well as their
combinations with BrEq/BrLT input signals have been
provided in the corresponding ROMs, and there are 48
elements in each ROM for testing
p But the Result ROM is empty, and you need to fill it with
correct results (each result corresponds to the set of control
signals that should be produced by the controller)
p See the EXCEL file ctr-result.xlsx for more details...
6Implement the Single-Cycle Processor
n The fetch stage has been given in addition to the input/output pins,
and the IMEM has already been filled with the Fib(6) program (our
processor lacks support for reading a parameter from keyboard)
n You need to implement the rest parts, some important issues include
p How to Halt the processor when encoutering the ECALL instruction?
– Hint: You can use the Halt control signal to disable clock input to PC,
therefore it will not be updated anymore