Hello, dear friend, you can consult us at any time if you have any questions, add WeChat: THEend8_
Note: Following questions are based off of the implementation used in Chapter 4 of the CO & D Book. (1 thru 14 are worth 4 points each). These questions are what you will see as part of the last test.
1. What are the Five Stages of a Machine Cycle?
2. Define the Data Path and Control Path.
3. Define Pipelining.
4. Does Pipelining increase Latency or Throughput? Why and How?
5. Define the following hazards
a. Structure Hazard
b. Data Hazard
i. Give an example of two sequential instructions that would present a Data Hazard
c. Control Hazard
i. Give an example of two sequential instructions that would present a Control Hazard
6. Define Stall on Branch
7. Define Two types of Branch Prediction and explain how each helps performance.
8. What are exceptions and interrupts? Is there a difference?
9. What were they originally created for?
10. What is the EPC register and Cause register? How are they used?
The remaining questions are from Chapter 5 of CO&D
11. Define Temporal and Spatial Locality
12. Give a basic explanation of memory hierarchy.
13. In your own words, describe the difference between Direct mapped, Set associative and Fully associative cache.
Chapter 1, Performance
14. In the equation above, CPU time can be reduced by reducing Instruction Count, CPI and/or Clock Cycle Time. In your own words, please explain different strategies or tools that can be used for reducing each.
15. Computer A has an overall CPI of 1.3 and can be run at a clock rate of 600MHz. Computer B has a CPI of 2.5 and can be run at a clock rate of 750 Mhz. We have a particular program we wish to run. When compiled for computer A, this program has exactly 100,000 instructions. How many instructions would the program need to have when compiled for Computer B, in order for the two computers to have exactly the same execution time for this program?
16. 15. (20 points) This question shows that you understand how the Data Path and Control work for the following given instruction.
lw $t0, 16($s0) # Load a word in memory into the register $t0.
# Assume the value being loaded from memory is 0x2A
# Assume the PC is at 0x00400004
# Assume that $s0 holds the value 0x10010000
Provide the following information.
A. Draw the Data Path in Red.
B. Along your defined Data Path, everywhere that it says “Instruction[##-##]”, identify what that data represents and the actual value of that data (in hex). For any “Instruction[##-##]” that is not a part of the data path for this instruction, leave it out.
C. Identify what two datum are going into the ALU and what data is coming out of the ALU.
D. Which of the “Write Data” destinations is used in this instruction? What value is written?
E. Give the value for each Control Signal. (RegDst, Branch, MemRead, MemtoReg, MemWrite, ALUSrc, RegWrite)
F. Give the ALUOp (Alu Operation) that will be performed. (Add, Sub, Shift, …)
16. (8 Points) For the MIPS datapath shown below, two lines are marked with “X”. For each one:
● Describe in words the negative consequence of cutting this line relative to the working, unmodified processor.
• Provide a snippet of code that will fail
• Provide a snippet of code that will still work
17. (8 Points) If the following three instructions are executed in a pipeline, there will be a stall before the second and third instruction can start. Explain the cause of the stall and show the actual stall using *** Assume $s1 already hold a value and $t0 holds an address. (Refer to zyBooks for examples on stalls).
Instruction Pipeline stage Cycles
lw $s2, 0($t0)
add$s1, $s1,$s2
addi $s2,$s1, 42
Instruction Line |
T1 |
T2 |
T3 |
T4 |
T5 |
T6 |
T7 |
T8 |
T9 |
T10 |
T11 |
T12 |
T13 |
T14 |
lw |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
add |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
addi |
|
|
|
|
|
|
|
|
|
|
|
|
|
|