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This lab is to be performed individually. We will carefully monitor all submissions
for plagiarism and any instance of plagiarism will be reported to administration.
In this Lab assignment, you will implement an cycle-accurate simulator for a 5-stage pipelined
MIPS processor in C++. The simulator supports a subset of the MIPS instruction set and should
model the execution of each instruction with cycle accuracy.
The MIPS program is provided to the simulator as a text file “imem.txt” file which is used to
initialize the Instruction Memory. Each line of the file corresponds to a Byte stored in the
Instruction Memory in binary format, with the first line at address 0, the next line at address 1
and so on. Four contiguous lines correspond to a whole instruction. Note that the words stored
in memory are in “Big-Endian” format, meaning that the most significant byte is stored first.
The Data Memory is initialized using the “dmem.txt” file. The format of the stored words is the
same as the Instruction Memory. As with the instruction memory, the data memory addresses
also begin at 0 and increment by one in each line.
The instructions that the simulator supports and their encodings are shown in Table 1. Note that
all instructions, except for “halt”, exist in the MIPS ISA. The MIPS Green Sheet defines the
semantics of each instruction.
Instruction Format OpCode (hex) Funct. (hex)
Addu R-Type (ALU) 00 21
Subu R-Type (ALU) 00 23
Lw I-Type (Memory) 23 -
Sw I-Type (Memory) 2B -
Beq I-Type (Control) 04 -
Halt Custom instruction FF
Special Note about Beq Instruction:
For the purposes of this lab only, we will assume that the beq (branch-if-qual) instruction
operates like a bne (branch-if-not-equal) instruction. In other words, in your implementations you
will assume that the beq jumps to the branch address if and jumps to PC+4
otherwise, i.e.,.
(Note that a real beq instruction would operate in the opposite fashion, that is, it will jump to the
branch address if and to PC+4 otherwise. The reason we had to make this
modification for this lab is because to implement loops we actually need the bne instruction.)