Hello, dear friend, you can consult us at any time if you have any questions, add WeChat: THEend8_
|
Instruction set design. Piplelined data path and control. Cache and memory system design Input/output subsystems. Software/hardware interactions. Parallel processing.
Instruction set architecture
Load/store architecture vs. x86
Simple MIPS datapath/control design
Pipelined datapath and control for integer instructions
Compiler optimizations for pipelines
Exception handling in pipelines
Introduction to multiple instruction issue
Floating point pipelines
Branch prediction and target address delivery
Caches and memory hierarchy
Impact of cache size, block size and associativity on performance
Cache simulations and software interactions
Interactions with virtual memory
Hardware support for operating systems
Input/output subsystem
Interactions with memory system and OS
Performance issues
Course requirement: Required course for Computer Science majors
Credit hours: 3
Classroom/Schedule/Venue: Mon: 4 pm – 6.45 pm, TH 327
Instructor |
Course No. |
Office location |
Office phone |
|
Office hours (Consultation) |
Dr. Vidhyacharan
Bhaskar |
CSC 656 |
SCI 255 |
TBA |
[email protected] |
Monday (3 pm – 4 pm) (Or by appointment) |
Text books:
Prerequisites by Topic
· A Grade C or better in CSC 415 (may be taken concurrently) or by the consent of the Instructor.
Student Learning Objectives
At the end of this course students will be able to
1. Understand principles of instruction set architecture.
2. Understand and extend simple pipeline implementations.
3. Understand in detail – cache, memory system behavior and design.
4. Estimate performance benefits from compiler optimizations and code transformations.
5. Develop simple trace-driven simulators for functional units.
Course topics:
The objectives of this course includes:
• Teaching principles of instruction set architecture
• Teaching pipelined data path and control design
• Overview of floating point support and branch handling
• Overview interactions between compiler optimizations, OS, and architecture
• Examining cache and memory hierarchy design
• Studying effects of code constructs on memory system behavior and performance
• Overview of common input/output technologies and operations.
Students will work on projects/assignments involving detailed instruction and memory system traces, to develop good understanding of how software constructs consume hardware resources. Students will make simple extensions to functional units to study the effect of design choices on performance. A strong background in computer organization/architecture is the key to doing more advanced work in operating systems and performance modeling/evaluation.
Evaluation methods
Four Handwritten/Computer Projects – 4 x 8 = 32 points
Three Quizzes – 8 + 10 + 10 = 28 points
One midterm exam – 15 points
One Final exam – 20 points
Attendance + Class Participation – 5 points
————-
Total – 100 points
————-
Mid-term and Final exams:
Mid-term exam will be conducted towards the end of October.
Final exam will be conducted as per the SFSU Fall 2018 Final exam schedule