EEC180 — DIGITAL SYSTEMS
FINAL EXAM
1. COUNTERS (25 POINTS)
Consider an 8-bit binary counter with the following specifications:
• The counter has a clock input as well as two synchronous inputs M and reset.
• The counter has two outputs: an 8-bit unsigned number count and a 1-bit saturated.
• If M= 0, the counter counts up. However, when count = 255, the counter is considered sat- urated and it holds its count at 255 as long as M = 0.
• If M= 1, the counter counts down. However, when count = 0, the counter is considered saturated and it holds its count at 0 as long as M = 1.
• The saturated output is set to 1 when the counter is saturated.
• The counter resets (count = 0) when reset = 1. Write a Verilog model for the counter.
2. FSM IMPLEMENTATION (25 POINTS)
Consider the state diagram shown below.
1. Design a circuit (with input x and output z) that implements the above state diagram and uses one-hot encoding for the state assignment. Assume that the only available components are D flipflops (with both Q and Q outputs) and 2-to-1 multiplexers. Make sure to use the minimum number of multiplexers. (10 points)
2. Write a verilog model for a D flip-flop (with both Q and Q outputs). (3 points)
3. Write a verilog model for a 2-to-1 multiplexer. (2 points)