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Inf2C Computer Systems
Coursework
The aim of this assignment is to write a simulator for a 5-stage multi-cycle MIPS
processor with a simple, direct-mapped cache. A simulator is nothing more than a
functional model of a processor that mimics the behavior of a real processor but is
written in a high level language. Your simulator, written in C, will read a memory
file consisting of MIPS instructions and data, “execute” the instructions and output
the state of the processor and various statistics for the cache during the execution. To
get you started, you will be provided with a skeleton implementation of the simulator
that you will need to extend. You are strongly advised to read up on MIPS processor
and caches in the lecture notes and course textbook and to commence work as soon as
possible.
This is the second of the two assignments for the Inf2C-CS course. It is worth 50% of
the coursework marks and 20% of the overall course marks.
1 Overview
In this assignment, you are provided with a skeleton of the simulator, which includes
the 5-stage MIPS processor and memory. You will need to extend the provided code
to support a set of specified MIPS instructions (Task 1) and add a cache between the
processor and the memory (Task 2).
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Skeleton Organization: The skeleton is broken down into four source code files. Each
file accomplishes particular tasks. You are allowed to modify and submit only certain
files. The functionality and permission to modify for each file are described in Table 1.
Filename Functionality Modifiable
mipssim.c Multi-cycle MIPS processor (datapath + control) Yes
mipssim.h Data structure definitions for datapath No
memory hierarchy.c Memory hierarchy implementation Yes
parser.h Reading and parsing input files No
Table 1: Source Files
mipssim.c: This file describes the multicycle MIPS processor as studied in class.
The processor consists of the following core components: PC, Pipeline registers (IR, A,
B, MDR, and ALUOut), Programmer-visible registers (in the register file), ALU, ALU
Control, and Control.
The processor’s functionality can be broken down into the following logical stages: instruction fetch, decode and read RF, execute, memory access and write back. Note that
each stage updates some architectural or microarchtictural state. For instance, the instruction fetch stage updates the IR. The write back stage updates the RF.
Furthermore, this file handles the Control component by implementing a finite state
machine. The state machine can be found in a function named FSM.
mipssim.h: This file defines the following required data structures for the MIPS
processor:
• ctrl signals, which control the datapath and are updated on a cycle-by-cycle basis
by the control FSM
• instr meta, which stores information about the instruction currently stored in the
IR
• memory stats t, which consists of memory stats for loads, stores and instruction
fetches
• pipe regs, which includes the PC and microarchitectural registers of the processor
(IR, A, B, ALUOut and MDR). For convenience, we refer to these registers as
pipeline registers to indicate that they are spread out over the datapath (unlike
the programmer-visible registers, which are all located inside the register file).
On any given cycle, the complete state of the processor is stored in a structure called
architectural state. This structure includes the current clock cycle since the start of
execution (clock cycle), state of the current instruction’s execution (e.g., INSTR FETCH
or DECODE), current values of control signals (control) and memory stats (mem stats).
This structure also includes an array of registers, which models a register file, as well
as the memory. Finally, architectural state also includes the pipeline registers, which
are maintained in two pipe regs structs: curr pipe regs and next pipe regs. The former
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(curr pipe regs) is used within a cycle to read the value of a given register. Meanwhile, a
value that needs to be written into a pipeline register at the end of the cycle should be
stored in next pipe regs. At the end of each clock cycle, curr pipe regs is updated with
values from next pipe regs; this functionality is already provided for you.
IMPORTANT: your program must ensure that the state of the processor as represented by architectural state is correct on any given cycle. To accomplish that, you must
maintain the control signals, curr pipe regs, mem stats, registers and memory. These updates must happen inside the designated functions in mipssim.c and memory hierarchy.c.
memory hierarchy.c: This file provides the memory interface via two functions:
memory read, which is used for reading from memory and memory write, which is used
for writing to memory. By default, reads and writes access the memory directly, i.e.,
there is no cache.
parser.h: This file contains the implementations of reading instructions and data
from input files. The format of input files are described in Sec 5.
Figure 1: Multi-cycle MIPS processor
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2 Task 1: MIPS Processor
In the first task, your job is to complete the datapath of a MIPS processor provided
in the skeleton mipssim.c. Figure 1 illustrates the processor datapath and the control
signals. In the skeleton, there are five functions: instruction fetch, decode and read RF,
execute, memory access and write back, corresponding to the five stages of the processor.
Some of these functions are incomplete, and you need to implement them according to
the MIPS data and control paths as specified in the P&H chapter on the multi-cycle
processor (available on Learn).
Additionally, you are required to complete the Control implementation in mipssim.c.
In every cycle, the Control component controls the state of each stage of the processor
using a finite state machine (FSM). Figure 2 illustrates the FSM used in the Control
component of the multi-cycle MIPS processor as discussed in class. Note that the names
of the states in Figure 2 may be different from the source files provided to you. Each
circle in Figure 2 corresponds to one state of the FSM and lists (1) the values for mux
select signals that are set in that state, and (2) all enable signals that are set in that
state. For instance, State 0 (i.e. instruction fetch) shows that enable signals MemRead,
IRWrite and PCWrite must be set.
In the skeleton, a global struct named arch state.control contains the control signals
generated by the Control component. You must use these signals and complete the
FSM function to control the 5 stages. You may add new FSM states if necessary.
The skeleton already implements both the datapath and the control for the ADD
instruction. Your task is to extend the code to support the following instructions: LW,
SW, ADDI, J, BQE and SLT. Note that Figure 2 does not show the required states and
transitions for an ADDI instruction. You must design the state machine for ADDI by
yourself (Hint: ADDI is similar to ADD except it has one different operand).