ELEC373 Synthesising the NIOS II Processor
Synthesising the NIOS II Processor
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ELEC 373 Assignment
Synthesising the NIOS II Processor
Assignment Outline
In Assignment 3 you added some extra instructions to a MIPS processor which was then synthesised
and executed on the DE2 board. This assignment aims to introduce you to a commercial synthesised
processor targeted for Altera FPGAs, which allows the easy importing of peripherals and the use of
an industry standard IDE for software development.
Assignment 4 is split into two parts, Parts A and B. The objective of Part A is to get you familiar
with QSYS, the NIOS II Processor and interfacing SRAM and SDRAM, on the Altera DE2 Board,
to the NIOS II processor you synthesise. Part B requires you to develop and test a Custom
Instruction that will be implemented in the FPGA.
Part A – SRAM & SDRAM
The NIOS II hardware development tutorial synthesises a NIOS II processor with, 20 KB of on-chip
memory, a timer, a JTAG UART, 8 parallel I/O pins and a system ID Component. Part A of this
assignment requires you to interface the 512 KB SRAM and 8 MB SDRAM on the Altera DE2
Board to this design.
You should then test that the memory is functioning correctly by running the Memory Test programs
available within the NIOS II IDE. You should modify the Memory Test Programme so that your
Name and ID number are shown in the terminal window each time the memory is tested.
Hints
1. Initially use the altera_up_avalon_sram Controller (SRAM/SSRAM) for the SRAM interface
2. Use the SDRAM controller for the SDRAM Interface
3. Add a PLL to advance the clock for the SDRAM by 3ns compared with the system clock.
Part B – Custom Instruction
Part B requires you to develop a Custom Instruction to count the number of leading 1s (or 0s – see
Table 1) in the 32 bit number passed to the instruction (for example 0xFF000000 would have 8
leading 1s and 0 leading 0s, whilst 0x00F00000 would have 0 leading 1s and 8 leading 0s). You
should write a program to test your Custom Instruction. You should also develop a test routine in C
or assembler that performs the same function as the Custom Instruction and compare the speed of the
Custom Instruction against your software implementation.
Submission
You report should include the following:
1. Block diagram of BDF developed in Part A.
2. Table showing memory Map for Part A
3. Screen dumps of test results showing memory test programs working for SRAM and
SDRAM
4. ASM(s) and Verilog code for your custom instruction in Part B
5. C/C++ for your test program of Part B
6. Screen dump showing the results of your program for Part B
7. Results showing a speed comparison between the Custom Instruction and your software
implementation.
8. Explanation of your results.