Hello, dear friend, you can consult us at any time if you have any questions, add WeChat: THEend8_
EEE335/EEE348 Digital Coursework
The Task
Your task is to design a CMOS logic gate to implement the logic function below (based on the last digit of
your student Number, simulate it in LTSPICE and assess its performance.
Last Digit of Student Number Logic Function
Odd = ( + ̅. ̅).
Even = (̅ + . ) + ̅
You should implement your design within the basic spice design file that accompanies this assignment (Digital
Spice Design.asc). This provides a framework that you should use. It has 4 pulse generators (for generating
the 4 inputs to your circuit). The outputs from these generators pass through two minimum sized inverters.
The waveforms from the generators approximate to a binary number “DCBA” and cycles from 0000 to 1111,
etc. across a 5s period. There are small offsets of 5ns between each of the waveforms to make them more
interesting. You are free to change the sequences of values applied to your circuit.
The outputs of the 4 pairs of inverters are labelled A, B, C, D. These MUST be the inputs that you drive into
your circuit for the function that you are implementing.
The output of the function, Y, from the circuit you implement should be connected to a 50fF capacitor (this is
also in the basic spice design file).
To reiterate, you should only connect to VDD, GND, A, B, C, D, and Y in the basic design file. You will note that
Vsupp is a parameter in the set of directives and it is set, currently, to 3.3V. This is used to generate VDD
(which you will use in your circuit), Vdriver (which is used, separately, to supply the inverters that generate A,
B, C, and D), and the pulse voltages generated in V1, V2, V3, and V4. You can change Vsupp in the directive
and all the voltages generated will change together.
The transistors in your design should be taken from 5827_035 library.
The circuit you design should try to optimise the area and performance of your circuit:
1. Area is, essentially, the W*L for all the transistors in your design (do not include M1..M16 in your
estimation of Area);
2. Time should be measured as the worst-case time between any of the inputs passing switching voltage
(VDD/2) either rising or falling and the output voltage passing the same (VDD/2) as a direct
consequence of the change of input voltage.
You will need to submit a report (maximum 5 pages, 11pt text, normal margins) to include the following:
• A clearly labelled diagram of your circuit design from SPICE, and a short description of it. You do not
need to include the voltage generators but the signals going into and out from your actual design
should be labelled (please make sure that any text on it is readable).
• A justification that your design meets the specification. Please ensure that you include the sizing of the
transistors.
• A plot of the propagation delay (Time) between the D input and the Y output as the power supply
voltage, VDD, is varied between 0.9V and 3.3V (in steps of 100mV). HINT: you might want here,
to set the values of other inputs to ensure that Y is changing only as a consequence of a change
in D.
• A plot of the energy consumed by your circuit over the 5us period of the simulation as the power
supply voltage, VDD, is varied between 0.9V and 3.3V (in steps of 100mV). You will need to think
carefully about how to measure the energy going into your circuit. You MUST use the input
waveforms, as supplied, for this exercise.
You also need to submit a functioning LTSpice schematic file (this does not form part of the assessment but I
may simulate it if I think there is an issue).
Please, also, quote the last 3 digits of your Student Number in your report.
The deadline for submitting the report and the LTSpice schematic file is Sunday 8th January 2024 at 23:59pm.
Rubric for Assessment
Your report (and work) will be assessed according to the following rubric:
Category An excellent report will… Weighting
Technical
content
Introduction • Set out your project’s aims and specification. 15%
Design and
methodology
• Explain how you designed your circuit and
optimized it, so that someone reading your report
could repeat your work
• Justify your design decisions with relevant
information.
25%
Results
• Present a set of results that enable you to
assess your design against the project aims and
specification
• Provide a logical written interpretation of your
results.
20%
Discussion
and
conclusions
• Critically compare your results against the
project aims and specification
• Comment on any shortcomings of your design,
and discrepancies from theory
• Summarise your project and highlight the key
achievements.
15%
Style
Structure and
formatting
• Follow a logical, narrative structure
• Be professional, with appropriate use of fonts,
contents and title pages, paragraphs, sections,
sub-sections etc.
5%
Figures and
plots
• Use figures and plots that are correctly sized,
clear, well-labelled, and captioned
• Make intelligent use of figures, with each figure
adding detail and information that would be
difficult or impossible to convey in writing.
10%
Writing clarity • Make good use of English and be easy to read. 5%
Referencing
• Provide appropriate, IEEE-formatted references
• Use references to websites only when book or
journal references are not available.
5%
REMEMBER: This is a graded assessment for EEE335 (and the first half for EEE348), where a score
of 50% equates to a 1st class mark for the module. You will need to demonstrate real
understanding of the material to access the higher marks.