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Interrupts with the AXI TimerIntroduction
创建日期：2024-04-30 16:28:14
标签： LAB 4
Interrupts with the AXI TimerIntroduction

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LAB 4 : Interrupts with the AXI TimerIntroduction

This lab introduces the interrupt structure of the ARM processor using the AXI timer. Interrupts
allow a processor to respond to externally generated events, temporarily halting its current execu-
tion and jumping to subroutine which is written to service the interrupt. Upon completion of the
interrupt service routine, program control resumes from where the processor was interrupted.
As briefly mentioned in Lab 3, the AXI timer can be configured (either in Generate mode or Cap-
ture mode) to generate a pulse for one clock cycle on its external Interrupt port. This Interrupt
port of the AXI timer will be connected to the Interrupt Request pin of the ARM processor using
XPS. The ARM processor contains hardware (General Interrupt Controller) which is designed to
assist the processor in responding to interrupts. Software will be written to configure the interrupt
controller and to bind a user-written C++ function to the Interrupt Handler which will be executed
every time the interrupt occurs.
Setting up the user Linux environment:
1. Type the following on a terminal:
source /CMC/tools/xilinx_14.7/14.7/ISE_DS/settings64_CMC_central_license.csh
This sets up the Xilinx environment
Launching PlanAhead:
2. Launch the planAhead tool from your COEN317_LABS/Lab4 directory:
planAhead &
Create a new project from PlanAhead:
3.1. File -> New Project
3.2. A window pops up, select Next
Give your project a name and choose the desired project path.
Project name: lab4
Project location: .../COEN317_LABS/Lab4
Leave the “Create project subdirectory” checked
Select Next
3.3. RTL Project should be selected. Keep the selection.
2
Select Next3.4 We do not need to specify any sources, select VHDL as the target language in the drop down
box:
Target language: VHDL
Select Next
3.5. We do not need to specify any IPs. Select Next.
3.6. We do not need to specify any UCF files for this part. Select Next.
3.7. Select the ZYNQ-7 ZC702 Evaluation Board for the project:
Select Boards
Scroll down the list and choose ZYNQ-7 ZC702 Evaluation Board
Select Next
3.8. Review settings and Select Finish
Create an embedded processor project with the Add Source wizard:
4.1. On the left panel under Project Manager, select Add Sources.
4.2. Choose Add or Create Embedded Sources and select Next
4.3. Select Create Sub-design
A window will open prompting to enter a module name. Name it “system”
Module name: system
Select OK
Select Finish
Designing the system in XPS:
XPS will be used to design the system consisting of an AXI timer and its associated AXI intercon-
nect. The Interrupt port of the timer will be connected to the processor’s interrupt request pin.
5.1. A window pops up and asks:
This project appears to be a blank zynq project.
Do you want to create a Base System using the BSB Wizard?
Select Yes
5.2. The BSB Wizard asks for additional settings
The AXI System should be selected by default with no other parameters.

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EARN 5 FE 825 IERG 5130 STAT 8178 EE161 ADS2 G54FUZ CS326 113B ECN 226 QBUS6860 ELEC3202 COMP9334 MGT11B MET CS 777 STA238 00099F Python SMM306 CMT206 EC116 SP MAST90084 CS480/680 BCPM0091 CMPT 300 ECON2209 FY20 STAT 432 CVEN9625 MATH1712 CMP9771M CMP3750M CIS 325 AI506 MAT344H1S MGT7180 PSTAT 160B CSYS5010 1D STAT 453/558 ME152B STA304H1F CSCI-128 ME428 CO3002 FINE 7640 COMP3234 ECSE 223 EE497 – 3D MATH5905 ECS648U ENG5009 MATH10242 EC665 A CPI221 ISOM5220 MACE40402 MGT B456F COMP9315 AFM 113 STAT 778 CS 564 MA231 CS 230 CS 124 COMP5511 CSC317 ITEC1010 ELEC207 INFT 3019 7CCMFM06 EE 161 5G ECLT5810 MATH 7349 CS526 O2 COMP90054 ELE00063M ACCT5034 ARC1015 CSCI 40 CSCI E40 FIN 524B CS 462 389COM CMT309 MFIN703 COMP4250 STA304 STA304H1S STA 1003 FIN 448 BUFN 732 CS520 CVEN3701 ECMT6006 PHAS0100 CSIT314 MDIA 5028 CSCI 2134 MAT 451 CMPT 459 STAT 457 INFO20003 COMP4141 IELE8066 F540 ECM9 CSE 6321 FIN 430 MATH3911 BFC5916 COMP1011 EEE 6209 STATS 240 CW3 COMP206 COMP1003 4331W ISE 530 CMPT 295 MATH 239 QF5203 INFR08010 IT114105 FIT2093 ECON3124 ECON1195 MATH 337 STAT 3006 COMP202 COMP3130 MATH3609 COMP 250 CS6140 IEEE ELE00041I FIN40090 CIV 5899 MATH3066 IGNMENT MATH 2009 STAT3405 HIST 101 MATH 3281 CEGE0042 ICT532 LAB 7 LAB 5 MCO455 CSIT214 Q4 IFB104 A1 ECO220Y5Y DA5020 CMPSC473 FIN9007 DSCI553 MSCI534 COMP3308 CSE-112 CMPT 310 EE104 F 2C P20 ALY2010 BUSM060 STA258 ECO00030M R BIOSTAT 274 COS6012-B FIT3155 CMPUT 340 EC421 INFS4205 ECOM135 NATS 1740 COMP809 MBE 6005 STA465 CSSE2310 CIVL2700 DATA4700 CMPSC 473 ISE 529 CS5044 MAST30020 COMP2207 ENGG1001 COMP0046 FIT3165 STAT GR5241 MECH0007 vATHK1001 ANALYTIC ATHK1001 MATH352001 HW3 S1 BMAN 24662 COMP 636 Stat-461 STAT 302 STAT 2132 STAR534 ENG4137 CMP3752M CS3103 BISM3222 STA 135 ME155A IIMT3601 ECON3371 ECON 3371 HW4 FINA 5840 DT211C CTEC3902 MAT005 MATH2148 S261F Econ 332 MATH3734 MIS41270 7CCMFM13 SYST 664 CIS434 CENG10014 MT4111 MT4527 ECMM424 CMT219 Math 136 MATH 3120 COMP10002 MAST20009 MATH0058 BEEM117 ISYE 6420 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MATH20602 COMP532 MAS275 COMP5318 COMP4002 FIT5086 MAST20004 FIT3152 FIT5129 CIS2380 CS521 COMP 1005 EECMS CITS5501 ECE 462 ECON 6002 ENG 4051 CSC 648 CMT654 MECHENG 713 PHYS1002 AMME 2000 FP0060 DDES3200 MECHENG 743 BINF90002 FIT2081 ISYS90081 ELECTENG 722 BUS 360 ECOS3010 BUS2810 ETF2100 ENG2048 STAT5002 COMP2017 CEME 2003 MATS3004 COMP9319 PHYS1001 COMP5349 AMME2261 COMP-381 FIT3173 COSC2757 ENG4025 QBUS2820 COMP9414 MATH2021 EOSC118 MFIN6690 PMATH 321 CSE-141L MATH575A COMPSCI5002 COMP1511 management comp2123 FINS3616 COMP 3331 COMS30034 DTSC 71 AcF 702 AcF702 DTSC71 MAT021 ELE8083 ACFI213 EG-127J 127J FIT5163 FIT2001 ELE00113M CMT310 CS 245 ENGL 1101 MTH6115 EE497 CS 325 Math 124A MTH5130 MBA502 MGT 5380 ARCH 1261 F033800 20LLP109 ELE4009 FINANCIAL COMP3331 Computer ECE4179 20T3 COMP9311 COMP9311 UNSW MFIN6210 ACCT 5930 EE590 ENG2029 ECO100 SIT315 ACCT3610 COMP3600 STK2100 FIT2004 COMP30020 ACTL1101 Stat 101B BANA 200 COSC2473 ENGG1400 AI COMP90043 MMF 1914H PHYS 127 CS584 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