Hello, dear friend, you can consult us at any time if you have any questions, add WeChat: THEend8_
END COMP3467 Advanced Computer Systems Sample Exam 2020/21 Section A Q1 a) What features of the Hack architecture would make it an inappropriate model for simulating the performance of modern CPUs? [6 marks] b) Assuming a 12 bit address bus with a direct-mapped cache of 8 lines and a cache line size of 1 byte, what is the cache state after this series of read requests (addresses in decimal)? What is the hit rate? Assume that the cache is initially empty. 1 2 3 8 9 1 2 3 8 9 [9 marks] c) How does a set-associative cache differ from a direct-mapped cache? [3 marks] d) Find a series of requests for which the hit rate for a set-associative cache is at least twice the hit rate for a direct-mapped cache. [4 marks] e) What advantages and disadvantages are there in increasing the associativity of a set- associative cache? [3 marks] END Q2 a) What are load, store and fetch operations, and how are they related to the execution cycle of a CPU? [5 marks] b) A computer system contains both RAM and ROM devices. How likely would it be for load, store and fetch operations be carried out with each of these device types respectively? [5 marks] c) How does the number of registers in the CPU affect the frequency of load, store and fetch operations respectively? [3 marks] d) RISC processors are sometimes described as having a load/store architecture. What does this mean and how does it help to improve performance of the CPU? [4 marks] e) Some architectural features of modern processors improve average performance but degrade worst-case performance. Choose two such architectural features and explain why they behave in this way. How does this behaviour affect the type of application that these architectures are suited to? [8 marks] END Section B Q3 a) ‘Computer random access memory (RAM) is one of the most important components in determining your system’s performance.’ To what extent is this true? Where appropriate you should cite relevant articles (including web content). Max 1000 words excluding references. In your answer may wish to consider • The impact of memory performance on system performance • Steps that are taken to optimise memory performance • The interaction between memory performance and other architectural features • The impact of memory performance optimisation on other system characteristics [50 marks] COMP3467 Advanced Computer Systems Sample Exam 2020/21 Indicative solutions and mark scheme Q part Answer Mark allocated Q1 a) Memory responds within 1 clock cycle [1 mark] No cache [1 mark] Small number of registers: many more memory operations required [2 marks] no pipeline [1 mark] no FPU [1 mark] … or other reasonable answers(knowledge/comprehension) b) 1 (miss store line 1) 2 (miss store line 2) 3 (miss store line 3) 8 (miss store line 0) 9 (miss store line 1) 1 (miss store line 1) 2 (hit) 3 (hit) 8 (hit) 9 (miss store line 1) [2 marks] Hit rate 30% [1 mark] 12 bits. c=0, b=3, a=9 [1 mark] line 0 holds 8 tag 000000001 valid line 1 holds 9 tag 000000001 valid line 2 holds 2 tag 000000000 valid line 3 holds 3 tag 000000000 valid line 4-7 invalid [5 marks] (comprehension/application) c) Set associative cache has more than one line associated with each “b” value [1 mark], multiple tags compared simultaneously [1 mark]. Line replacement strategy required [1 mark] (knowledge/comprehension) d) Using same structure as above ( 8 lines, 1 byte per line) [1 mark] this series of requests would all be misses for direct mapped (hit rate 0%) [1 mark], but would give a hit for set-associative (hit rate 33%) [1 mark]: 0 8 0 [2 marks] (comprehension/application) e) Increasing associativity has implementation costs (more comparators required) [1 mark] but decreases likelihood of cache misses when the number of concurrently active clusters increases [1 mark] e.g. multicore [1 mark] comprehension f) Load, fetch, store all memory operations [1mark]. fetch reads instruction [1 mark] before decoding. Decoding decides whether load/store operation is required [1 mark] then Load reads data [1 mark], store writes data [1 mark]. 6 9 3 4 3 5 COMP3467 Advanced Computer Systems Sample Exam 2020/21 Indicative solutions and mark scheme Q2 Q3 g) Load: RAM v likely (main variable store). ROM unlikely but possible (e.g. string constants) [2 marks] Fetch: RAM likely (program loaded dynamically) ROM v likely (most ROM is program code) [2 marks] Store: RAM exclusively, can’t write to ROM. [1 mark] h) Increasing the number of registers means that more program variables can be stored directly in the CPU, reducing the number of load/store operations. [2 marks] More registers means larger instruction sizes, so possibly slightly increases the number of fetch operations. [1 mark] i) Load/store: no single instruction can do a load and a store [1 mark]. Breaking behavior down in this way helps the pipeline to function effectively (inc diagram) [3 marks] j) Any two examples e.g. pipeline, cache [4 mark]*2 • The impact of memory performance on system performance • Steps that are taken to optimise memory performance • The interaction between memory performance and other architectural features • The impact of memory performance optimisation on other system characteristics • Scope, appropriateness and analysis of sources referred to 5 3 4 8 5 10 5 10 20