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CMPSC473 Virtual Memory Management
创建日期：2024-04-08 17:31:50
标签： CMPSC473
Virtual Memory Management

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CMPSC473

Project 3: Virtual Memory Management
Please read this document carefully!
[Note: There are no checkpoints and the whole assignment is due at once. However, we will be
checking your incremental commits as a way of detecting possible violations of AI
requirements.]
Goals
The goals for this project are to help you:
1. Get experience working with a trace-based event-driven simulator
2. Get experience with a basic virtual memory management system (including MMU, TLB, DRAM,
DRAM-resident multi-level page tables, page replacement algorithms, and swap device)
3. Get experience with simulation-based performance evaluation
Project Overview
You will implement and experiment with a simple virtual memory manager (VMM) consisting of the
following elements: (i) MMU, (ii) TLB, (iii) DRAM, (iv) DRAM-based multi-level page tables, and (iv)
disk-based swap device. To do this, you will be given a simulator base code. If you have never worked
with a simulator, do not worry. Much of the simulator functionality will be already implemented in the
base code allowing you to focus on ideas related to VMM. Additionally, be sure to check out a short
video that has been uploaded in canvas announcements - wherein we describe all you need to know to
quickly become familiar with the base code.
Our base code simulates multiple processes time-sharing a single CPU with the help of the operating
system which implements a round-robin CPU scheduler. The code base has been written to work for
processes that only execute non-memory instructions. For each simulated process, the simulator reads the
instructions from an “input trace file” for that process. You will extend this to simulate the time-sharing of
processes that also execute memory instructions (such as loads and stores) that access virtual addresses
that need to be translated into their physical counterparts by the MMU.
As input, you will receive two types of files: input files and traces. These files are present in the ‘traces’
folder.
Where to find the simulator base code
The simulator base code is in the simulator.c file. You can compile it using the make command. Then, to
run the simulator, you need to write the following command:
$ ./simulator input1.txt output1.txt
Where input1.txt is the input file and output1.txt will contain the output from running the simulator.
Simulator Inputs
Our simulator takes two types of inputs for each simulation (henceforth also called “experiment”): (i)
system parameters and (ii) a scheduling trace for each process involved in the experiment. These inputs
are specified within a file that is passed as a command line argument to the simulator. So for an input file
called input1.txt, the simulator would be invoked as follows, where the output will be written to
output1.txt. More details on compiling and running the simulator appear under “Using the Simulator”
$ ./simulator input1.txt output1.txt
The format of an input file is as follows:
# list of system parameters specified as parameter-descriptive-string parameter-value; (all latencies
are in units of a “cycle”)
# list of parameters that will remain the same across all experiments
Non-mem-inst-length 1
Virtual-addr-size-in-bits 32
DRAM-size-in-MB 4
TLB-size-in-entries 16
TLB-latency 1
DRAM-latency 100
Swap-latency 10000000
Page-fault-trap-handling-time 10000
Swap-interrupt-handling-time 10000
TLB-type FullyAssociative
TLB-replacement-policy LRU
# list of parameters that may vary across experiments
P-in-bits 12
Num-pagetable-levels 3
N1-in-bits 8
N2-in-bits 8
N3-in-bits 4
Page-replacement-policy LRU
Num-procs 3
# trace-file-name arrival-time-of-process
process1 0
process2 3
process3 4
The processes are in order, meaning that each process has a start time later than or equal to the previous
start time.
Code for parsing this file will be provided with the functions openTrace(), closeTrace(), readNextTrace()
and readSysParam() in fileIO.h/c files.
The traces are: “input1.txt”, “input2.txt”, …., “input10.txt”.
Process trace files contain a list of addresses accessed by a program. The process trace file names will
correspond to trace-file-name.txt from input trace files. So in the above example the “input1.txt” points
to the 3 process file - “process1.txt”, “process2.txt” and “process3.txt”. ‘Mem’ or ‘NonMem’ is used to
define the type of instructions.
Here is an example of the first few lines within a process trace file:
Total-num-instr 1000000
Mem 0x12f00C00
Mem 0x77f46B77
NonMem
Mem 0x7ffde001
Mem 0x12f0015C
NonMem
Mem 0x77f3c000
Mem 0x12f00C28
NonMem
NonMem
NonMem
NonMem
Mem 0x12f00010
Mem 0x12f0CC11
Mem 0x12f00100C
Mem 0x77f3CDE1
...
Code for parsing this file will be provided with the functions openTrace(), closeTrace(), readNumIns()
and readNextMem() in fileIO.h/c files.
The process traces are available for each process in the traces: “process1.txt”, “process2..txt”, ….,
“process44.txt”.
Using the Base Simulator
We have simulated the Round Robin process scheduler in the schedulingRR() function. This is the only
scheduler you need to work with.
The base code simulates NonMem instructions ONLY and generates the following upon the completion
of an experiment:
1. per-process completion time
2. total number of context switches
3. total amount of time spent in OS vs. total amount of time spent in user mode.
The current implementation works with “input1.txt” and “input10.txt” only which has all NONMEM
instructions.
“input1.txt” has 3 processes: process1, process2 and process3. Each of these processes have 2, 2 and 3
NonMem instructions respectively.
Use the following commands to execute the simulator:
Make
./simulator input1.txt output1.txt
[here input1.txt is the trace parameter you wish to experiment with, output1.txt is the file name where the
output will be written]
Make clean will delete all object files.
The execution order of the processes in “input1” are: process1 → process2 → process3 → process2 →
process3; where quanta = 5, nonMemReadTime = 2 and contextSwitchTime = 1.
The below diagram shows the execution order of the 3 processes in “input1”:
What you need to do
You are required to append to this simulator to take care of all types of instructions and generate the
following: [You can use traces 2-9 as reference to test your code]
1. per-process completion time
2. total number of context switches
3. total number of disk interrupts
4. per-process and total number of TLB misses (absolute and ratios)
5. per-process and total number of page faults (absolute and ratios)
6. per-process and total fraction of time in blocked state
7. total amount of time spent in OS vs. total amount of time spent in user mode.
To that end, you would have to implement data structures for TLB and page table and include necessary
functions and helper data structures.
You must assume that the swap device has sufficient capacity to accommodate the active address spaces
in their entirety in any experiment. You will assume that the capacity needs of the page tables themselves
are accommodated by main memory other than the DRAM that the simulator considers (but that it has
similar latency characteristics). You will ignore the main memory needs of the page tables themselves in
your simulation of DRAM usage. You will assume that all the memory instructions in the trace files
reference valid virtual addresses and, therefore, do not raise traps. All page table entries must be aligned
to 4 Bytes. Besides the PPN, you only need to consider the valid bit within a PTE. All of these other PTE
entries in a real page table are to be ignored: permissions, user/kernel, dirty, reference.
Provided Code Structure
● dataStructures.h file contains the structs used in this project. You can add other structures here.
● fieIO.h/c file contains the helper functions for reading the traces.
● gll.h/c contains a linked list implementation for ease. It has been used in the existing code and
you are welcome to use it for your linked list implementation.
● simulator.h/c contains the code for the simulator. You are expected to include your
implementation in this file. There are //TODO instructions that give you some guidance about
adding your implementation specific values in existing functions. You are expected to determine
how to include your implementation yourself.
○ init() initializes all the data structures and list of processes. processList is the list of all
processes. Any process that becomes ready to run is moved to readyProcess list. The
process that should run right now is moved to runningProcess list. You should initialize
your necessary variables/data structures here.
○ simulate() function is the simulator which loops through all the processes until all of
them are done. It calls the processSimulator() function in a loop. processSimulator()
simulates the running process until one of these things happen- timer interrupt, disk
interrupt, page fault, process finishes. processSimulator() calls readIns() function that
reads the next instruction for the running process. You have to handle “MEM”
instructions in readIns() function.
○ diskToMemory() function moves one page from disk to memory. You have to implement
it.
To implement these functions, you will need to implement TLB and page table along with MMU
and swapping logic. You would also need to implement multiple page replacement
algorithms(described in next section).
● Recommended order of implementation:
○ MMU, DRAM, swap device, Page table only with no TLB
○ Add TLB
○ Performance evaluation.
Page Table Implementation (40%)
In this part of the assignment you need to implement a multi level page table with the following page
replacement policies:
● Optimal: The page that will not be used for the longest period of time in the future is to be
removed
● LRU: The least recently accessed page is the one to be removed.
● (BONUS) Clock: You should maintain a clock hand that rotates around memory. Each physical
page is marked "unused". Each time a page is needed, the hand advances until it finds a page
marked "unused", at which time that page is chosen for eviction. If it finds a page marked "used''
in this process, the page is changed to be "unused". In addition, on every memory reference, the
page accessed should be marked "used".
TLB Integration (20%)
In this part of the assignment you need to implement a simulation of the Translation Look-aside Buffer
(TLB) that uses the LRU replacement algorithm.
Performance Study (40%)
After completing and testing your implementation so far, you will conduct two types of experiments. You
will describe your findings in a project report (doc or pdf). We first describe these two types of
experiments followed by the contents of your project report .
Experiment type 1: In these experiments, you will simply run your simulator with the following inputs
and report the outputs described under “What you need to do”:
● List of system parameters to use.
○ Non-mem-inst-length 1
○ Virtual-addr-size-in-bits 32
○ DRAM-size-in-MB 1
○ TLB-size-in-entries 16
○ TLB-latency 1
○ DRAM-latency 100
○ Swap-latency 10000000
○ Page-fault-trap-handling-time 10000
○ Swap-interrupt-handling-time 10000
○ TLB-type FullyAssociative
○ TLB-replacement-policy LRU
○ P-in-bits 12
○ Frac-mem-inst 0.2
○ Num-pagetable-levels 3
○ N1-in-bits 8
○ N2-in-bits 6
○ N3-in-bits 6
● Report the below details for the process mixes in inputs 5-9 in the format specified:
Aggregate statistics:
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MAS316/414 ACCT2522 MSIN0181 ATMS 201 COMP3425 MATH7861 SOLA2060 MA 325 7CCEMCTH ECON 432 INFT2051 SOLA 2060 ECOS2002 Stats141XP BIOA02H3 S2022 MA4601 K5 COMP5329 EG 284 IB3A70 WECO1020 COMP3027 Energy ACS61011 MAST20026 STAT 533 MATA31 ENVS257 BEM2031 EC 486 COMP0172 CS3214 EECE5644 IB2B20 COSC2536 COSC1147 COMP6214 5CCM242A COMP0130 AMME2000 MTMG50: EG238 ACF6006 QBUS2810 COSC2391 ECON7560 MATH377 STA305 CS 486 COMP1117B EL648 ELEC3909 ECON 241 COMP 4901W BUSI4428 ENEN20002 ENGN4524 ELEC3115 CSC 413 PSYC 100B ECON1002 MATH256 ANSC20005 MTHS2008 MATH40082 COSC 2406 FIT3174 STA 238 CMT202 Differential Equations MTHM017 GARCH 101 MATH2069 CSC336S ACSC12 ETF2121 CEME 2001 DB B474F ARHT1001 EECS 3311 3220 STATS 786 CS 484 COMP20008 MATH4091 ECE 455 CSCI 204 BUS B200F BA 875 BU5562 COSC 1147 X11 GEOG 101 IMM250F CSE 584A MATH38172 LAB 4 ELEC5882M FINS5523 EE 430 COMP 465 6CCS3PRE 7CCSMNSE FINANCE ACMB02H3 ENGG2112 ELEC5616 SCM B371 CHEM3120 CS22 ECMT2130 MAST30011 ADSPBF706 CENG0013 ACCOUNTING BUSS1040 CHEM 181 MAT136H1 GY 6183 COMP3170 AGRI90089 PHYSICS 1002 ECON10003 IEOR E4004 ACS61012 MATH 40550 MKTG2113 TELE4653 ENSC1004 ECE 232E MK726 MTRX2700 SHEET 3 CSCA08 COMP30027 Math 2XX3 statistic MMAN3200 BISM7213 ECMM109 ECON 2022 FNCE 20005 GR5067 CSCB09 ME 3017 CS 5100 PHYS 2903 COMS 4771 COMP222 COMP 1046 CSC148H1 ISYS2038 FINS2615 OT5206 COMP2048 A6 MECH5770M MA826/20 CMPT 726 STA457 INFS6071 INFS588 integral ECON 216 IRDR 0017 MA323 PA 15213 PSYC2001 ENV222 Statistics ACCT5930 ACCT12 LAND2121 ME 5405 COMM1180 TELE3113 A7 ECE 568 ACCT2019 INFS1200 ENGG1340 CS 1400 ASST3 FINM7409 SWEN30006 INFO2222 FIN20150 SOSS1000 CSSE7231 FINS5513 COMS3200 CECN 702 ECON4060H MN3515 HW2 PSYA02H3 ECON 2112 COMP90051 CS 1652 MA30059 AF1605 MKTG7501 ECO-6003B COM4521 CTM ECON3350 COMP 3804 ELEC9762 BISM 7255 ST22 MATH20014 MNE3122 COMP343 MATH5165 ELE7029 ENGR30002 SEEM3500 ECON7350 RISK5002 FINM7405 COMP90059 MOS 3320B STAT 431 BISM7221 MATH3014 MTH783P EBA 35302 ACS133 BUS2206 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