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CMPT 295 Assignment
创建日期：2024-04-08 14:48:43
标签： CMPT 295
Assignment

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CMPT 295

Assignment 7
Objectives:
 Designing and evaluating instruction sets (ISA)

Submission:
 Submit your document called Assignment_7.pdf, which must include your answers to all
of the questions in Assignment 7.
o Add your full name and student number at the top of the first page of your
document Assignment_7.pdf.
 Submit your assignment Assignment_7.pdf on CourSys.

Due:
 Thursday, March 25 at 3pm.
 Late assignments will receive a grade of 0, but they will be marked in order to provide
feedback to the student.

Marking scheme:
 The marks assigned to each question is indicated in [ ].
 This assignment will be marked for correctness.
 A solution will be posted after the due date.

Note 1: Clarifying Memory Model. If any of these terms are unclear to you:
o memory model
o memory size
o address resolution and
o word size
please, before starting this assignment and as part of your study, read the document
found at this link:


This document has also been posted below our Assignment 7.
Note 2: In our lectures, we designed and evaluated the instruction set called x295M. In this
assignment, we shall design and evaluate three (3) other instruction sets: x295, x295+
and x295++.
Be aware: All of these 4 instruction sets are different!

Instruction Set 1 – x295
A. Description of x295 instruction set architecture (ISA)
 Data size : 16 bits
 Memory model
o Size of memory: 212 × 16
 m = 12 -> this means that each memory address has 12 bits.
 n = 16 -> this means that the address resolution, i.e., the smallest
addressable memory “chunk”, is a memory “chunk” of 16 bits.
 Each memory “chunk” of 16 bits has a distinct memory address.
 This is not a byte-addressable computer
o Word size: 16 bits -> this means that when the microprocessor reads from/writes
to memory, it reads/writes 16 bits at a time.
 It is a coincidence that the address resolution and the word size have the
same bit value. These two are independent from each other.
o Number of registers: 0
 Instruction set (assembly and machine instructions)
o Maximum number of instructions: 16
 This means that we need a maximum of 4 bits to distinctly represent each
of these 16 instructions.
 Therefore, the size of the opcode field, in the machine instructions, will be
4 bits (24 = 16)
o Operand Model:
CMPT 295 – Spring 2021
 Memory (only) – only memory locations are operands, no registers are
used as operands except the register representing the stack pointer
 3-operand model
 In the machine instructions, the order of these operands is: Dest, Src1, Src2
o Memory addressing mode: Direct, Base and Displacement and Indirect
 These may not all be used in the instructions found in this assignment.
o Assembly instructions (defined so far) and their format and meaning:
 ADD a,b,c Meaning: M[c] <- M[a] + M[b]
 SUB a,b,c Meaning: M[c] <- M[a] - M[b]
 MUL a,b,c Meaning: M[c] <- M[a] * M[b]
 In these assembly instructions, the order of the operands is: Src1, Src2,
Dest.
o Machine code format:


4 bits 4 bits 4 bits
This format is made of 3 words, each word is 16 bits in length (word size). This
format must be used to form all three machine instructions corresponding to the
three assembly instructions listed above.
The bit patterns for the opcode are:
Opcode (instruction) Bit pattern (4 bits)
padding 0000
ADD 0001
SUB 0010
MUL 0011
… …
B. Evaluation of x295 instruction set
C program x295 assembly program x295 machine code
z = (x + y) * (x – y); ADD x, y, tmp1


SUB x, y, tmp2
0001
0000
0000

0010
0000
opcode Dest (12 bits) padding padding Src1 (12 bits) Src2 (12 bits)
CMPT 295 – Spring 2021


MUL tmp1, tmp2, z
(where tmp1 and tmp2
are memory addresses
holding temporary results)
0000

0011
0000
0000

Note: In the above machine
code, we will not be using
actual memory addresses in
the memory address fields
(fields in purple).
1. The first step in evaluating our x295 instruction set is to write an assembly program using
the assembly instructions defined by our x295 instruction set. This step has been done
for us and is displayed in the table above in column “x295 assembly program”.
Note that as we are performing this step, we are verifying that our x295 instruction set
contains sufficient instructions to allow us to write such program in x295 assembly code.
(Nothing for us to do in this part of our x295 instruction set evaluation.)
Once we have our x295 assembly program, we need to transform it into its x295
machine code equivalent. This step has been done for us and is displayed in the table
above in column “x295 machine code”.
Note that as we are performing this step, we are verifying that our x295 instruction set
contains sufficient instructions to allow us to write such program in x295 machine code.
(Again, nothing for us to do in this part of our x295 instruction set evaluation.)
2. The next step is evaluating our x295 instruction set is to execute (hand trace) our
assembly program or its corresponding machine code and using the metric (criteria) called
memory traffic, we count the number of memory accesses our program makes during its
execution. In other words, we count how many time the execution of our program
required a word (16 bits) to be read from or written to memory.
Note that as we are performing this step, we are verifying that the meaning of the
instructions contained in our x295 instruction set is such that hand tracing these
instructions does indeed produce the result the software developer that wrote the above
C program expected. This is to say that if we use the test case: x = 3, y = 2 when hand
tracing our x295 assembly code (or its machine code equivalent), we would obtain the
same (expected) result as if we were to hand trace the C program itself.
As part of this step in the evaluation of our x295 instruction set, we are asked to evaluate
the number of word size memory accesses made by the microprocessor when it is
CMPT 295 – Spring 2021
fetching and executing each assembly code statement (or machine code statement) listed
in the left column in the table below. Also we need to justify our count. Finally, let’s total
our counts. [2 marks]
x295 program
(in assembly and machine
code)
Fetch
(number of word size
memory accesses)
+
Provide an explanation
explaning the count
Execute
(number of word size
memory accesses)
+
Provide an explanation
explaning the count
ADD x, y, tmp1


0001
0000
0000
Count:
Explanation:
Count:
Explanation:
SUB x, y, tmp2


0010
0000
0000
Count:
Explanation:
Count:
Explanation:
MUL tmp1, tmp2, z


0011
0000
0000
Count:
Explanation:
Count:
Explanation:
Grand Total: Total: Total:
CMPT 295 – Spring 2021
3. We also evaluate our instruction set using the metric (criteria) called static code size:
o The code size of our x295 program is 3 instructions.
o And since each instruction is 3 word long, the code size of our x295 program is 9
words.
(Nothing for us to do in this part of our x295 instruction set evaluation.)

Instruction Set 2 – x295+
A. Description of x295+ instruction set architecture (ISA)
Considering the results of our x295 instruction set evaluation, one possible improvement in
order to reduce the number of memory accesses could be to reduce the size of the machine
instructions. Since these are made of an opcode and a memory address, we could introduce
registers which could hold these memory addresses and take less space (less number of bits)
to identify in the machine code than to identify the memory addresses.
With the idea of introducing registers, we specified a second instruction set architecture (ISA)
with the same components as x295, but with the following modifications:
 Memory model
o Number of registers: 8 x 16-bit registers
 This means that we need a maximum of 3 bits to distinctly represent each
of these 8 (23) registers.
 Therefore, the size of any register field, in the machine instructions, will be
3 bits in length.
 Each register contains 16 bits.
o The bit patterns for the registers are:
Register Bit pattern (3 bits)
r0 000
r1 001
r2 010
r3 011
r4 100
r5 101
r6 110
r7 111
CMPT 295 – Spring 2021
 Instruction set (assembly and machine instructions)
o Operand Model:
 Registers
o Assembly instructions:
 ADD rA,rB,rC Meaning: rC <- rA + rB
 SUB rA,rB,rC Meaning: rC <- rA - rB
 MUL rA,rB,rC Meaning: rC <- rA * rB
 LOAD a,rC Meaning: rC <- M[a]
 STORE rA,c Meaning: M[c] <- rA
o Machine code format:
Format 1:

This format is made of 16 bits (1 word) and it can be used to form the machine
instructions corresponding to the ADD, SUB and MUL assembly instructions.
XXX -> these X’s can be either 0’s or 1’s – they are not used by the microprocessor.
Format 2:

This format is made of 32 bits (2 words) and it can be used to form the machine
instructions corresponding to the LOAD assembly instruction.
XXX, XXXXXX and XXXX -> these X’s can be either 0’s or 1’s. – they are not used by
the microprocessor.
Format 3:

This format is made of 32 bits (2 words) and it can be used to form the machine
instructions corresponding to the STORE assembly instruction.
XXX and XXXXXX -> these X’s can be either 0’s or 1’s– they are not used by the
microprocessor.
When the microprocessor decodes the opcode for a LOAD instruction, it will
know where to find Dest and where to find Src (in the memory address located
in the least significant 12 bits of the second word composing this instruction). It
will also know to ignore all other bits (X’s) in the instruction.
Opcode
(4 bits)

XXX padding XXXXXX Memory address of
Src (12 bits)
Dest
(3 bits)
Opcode
(4 bits)

Dest
(3 bits)

Src1
(3 bits)
Src2
(3 bits)
XXX
Data manipulation
type of instructions
Data transfer
type of instructions
Opcode
(4 bits)

XXX padding XXXXXX Memory address of
Dest (12 bits)
Src
(3 bits)

CMPT 295 – Spring 2021
When the microprocessor decodes the opcode for a STORE instruction, it will
know where to find Src and where to find Dest (in the memory address located
in the least significant 12 bits of the second word composing this instruction). It
will also know to ignore all other bits (X’s) in the instruction.
Note: About ISA design principles: When creating formats to encode instruction
set …
 As few of them as possible were created.
 The fields that have the same purpose (such as Opcode, Dest and Src)
are placed in the same location in as many of the formats as possible.
This helps simplify the design of the microprocessor (its datapath).
The bit patterns for the opcode are:
Opcode (instruction) Bit pattern (4 bits)
padding 0000
ADD 0001
SUB 0010
MUL 0011
LOAD 1010
STORE 1011
… …
B. Description of x295+ instruction set
C program x295+ assembly program x295+ machine code
z = (x + y) * (x – y); 1010 000 XXX XXXXXX
0000

1010 001 XXX XXXXXX
0000

0001 010 000 001 XXX

0010 011 000 001 XXX

0011 100 010 011 XXX
CMPT 295 – Spring 2021

1011 XXX 100 XXXXXX
0000
1. The first step in evaluating our x295+ instruction set is to translate the C program into
 an assembly program using the assembly instructions defined by our x295+
instruction set and
 its corresponding machine code using the machine instructions defined by our
x295+ instruction set.
Our task is to complete the middle column (assembly code) in the table above. The
machine code has already been given. [3 marks]
2. The next step is evaluating our x295+ instruction set is to execute (hand trace) our
assembly program or its corresponding machine code and using the metric (criteria) called
memory traffic, we count the number of memory accesses our program makes during its
execution. In other words, we count how many time the execution of our program
required a word (16 bits) to be read from or written to memory.
As part of this step in the evaluation of our x295+ instruction set, complete the table
below. [4 marks]
x295+ program
(in assembly and machine
code)
Fetch
(number of word size
memory accesses)
+
Provide an explanation
explaning the count
Execute
(number of word size
memory accesses)
+
Provide an explanation
explaning the count
Assembly code:




Machine code:
1010 000 XXX XXXXXX
0000
Count:
Explanation:
Count:
Explanation:
CMPT 295 – Spring 2021
Assembly code:



Machine code:
1010 001 XXX XXXXXX
0000
Count:
Explanation:
Count:
Explanation:
Assembly code:



Machine code:
0001 010 000 001 XXX
Count:
Explanation:
Count:
Explanation:
Assembly code:



Machine code:
0010 011 000 001 XXX
Count:
Explanation:
Count:
Explanation:
Assembly code:


Machine code:
0011 100 010 011 XXX
Count:
Explanation:
Count:
Explanation:
Assembly code:



Machine code:
1011 XXX 100 XXXXXX
0000
Count:
Explanation:
Count:
Explanation:
CMPT 295 – Spring 2021
Grand Total: Total: Total:
3. We also evaluate our instruction set using the metric (criteria) called static code size. Fill
in the blanks in the statement below: [0.5 marks]
o The code size of our x295+ program is __________ instructions ( __________ words).
Instruction Set 3 – x295++
A. Description of x295++ instruction set architecture (ISA)
Would reducing the number of operands to the instructions in our instruction set decrease
the number of memory accesses the microprocessor does when fetching and executing our
program?
Would introducing another instruction, namely COPY, in our instruction set also decrease the
number of memory accesses the microprocessor does when fetching and executing our
program?
With the above two ideas in mind, we specified a third instruction set architecture (ISA) with
the same components as x295 and x295+, but with the following modifications:
 Instruction set (assembly and machine instructions)
o Operand Model:
 2 operand model
o Assembly instructions:
 ADD rA,rC Meaning: rC <- rA + rC
 SUB rA,rC Meaning: rC <- rA - rC
 MUL rA,rC Meaning: rC <- rA * rC
 COPY rA,rC Meaning: rC <- rA
 LOAD a,rC Meaning: rC <- M[a]
 STORE rA,c Meaning: M[c] <- rA
o Machine code formats:

Format 1:

This format is made of 16 bits (1 word) and it can be used to form the machine
instructions corresponding to the ADD, SUB, MUL and COPY assembly instructions.
Opcode
(4 bits)

Dest
(3 bits)

Src
(3 bits)
XXXXXX
CMPT 295 – Spring 2021
XXXXXX -> these X’s can be either 0’s or 1’s.
The bit patterns for the opcode are:
Opcode (instruction) Bit pattern (4 bits)
padding 0000
ADD 0001
SUB 0010
MUL 0011
COPY 1001
LOAD 1010
STORE 1011
… …
B. Evaluation of x295++ instruction set
C program x295++ assembly
program
x295++ machine code
z = (x + y) * (x – y);
1. The first step in evaluating our x295++ instruction set is to translate the C program into
 an assembly program using the assembly instructions defined by our x295++
instruction set and
 its corresponding machine code using the machine instructions defined by our
x295++ instruction set.
Our task is to complete the middle column (assembly code) and the right column
(machine code) in the table above. [5 marks]
2. The next step is evaluating our x295++ instruction set is to execute (hand trace) our
assembly program or its corresponding machine code and using the metric (criteria) called
memory traffic, we count the number of memory accesses our program makes during its
execution. In other words, we count how many time the execution of our program
required a word (16 bits) to be read from or written to memory.
As part of this step in the evaluation of our x295++ instruction set, complete the table
below. [4 marks]
x295++ program Fetch Execute
CMPT 295 – Spring 2021
(in assembly and machine
code)
(number of word size
memory accesses)
+
Provide an explanation
explaning the count
(number of word size
memory accesses)
+
Provide an explanation
explaning the count
... expand the table by adding as many rows as needed using the
row format seen in the tables above ...
Grand Total: Total: Total:
3. We also evaluate our instruction set using the metric (criteria) called static code size. Fill
in the blanks in the statement below: [0.5 marks]
o The code size of our x295++ program is _________ instructions ( _________ words).
Conclusion
Considering the memory traffic metric (number of memory accesses required by our test
program), which instruction set (x295, x295+ or x295++) produces the most time efficient
program? [0.5 marks]


Considering the static code size metric (number of instructions/words required to implement
our test program), which instruction set (x295, x295+ or x295++) produces the smallest
program? [0.5 marks]
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MATH20602 COMP532 MAS275 COMP5318 COMP4002 FIT5086 MAST20004 FIT3152 FIT5129 CIS2380 CS521 COMP 1005 EECMS CITS5501 ECE 462 ECON 6002 ENG 4051 CSC 648 CMT654 MECHENG 713 PHYS1002 AMME 2000 FP0060 DDES3200 MECHENG 743 BINF90002 FIT2081 ISYS90081 ELECTENG 722 BUS 360 ECOS3010 BUS2810 ETF2100 ENG2048 STAT5002 COMP2017 CEME 2003 MATS3004 COMP9319 PHYS1001 COMP5349 AMME2261 COMP-381 FIT3173 COSC2757 ENG4025 QBUS2820 COMP9414 MATH2021 EOSC118 MFIN6690 PMATH 321 CSE-141L MATH575A COMPSCI5002 COMP1511 management comp2123 FINS3616 COMP 3331 COMS30034 DTSC 71 AcF 702 AcF702 DTSC71 MAT021 ELE8083 ACFI213 EG-127J 127J FIT5163 FIT2001 ELE00113M CMT310 CS 245 ENGL 1101 MTH6115 EE497 CS 325 Math 124A MTH5130 MBA502 MGT 5380 ARCH 1261 F033800 20LLP109 ELE4009 FINANCIAL COMP3331 Computer ECE4179 20T3 COMP9311 COMP9311 UNSW MFIN6210 ACCT 5930 EE590 ENG2029 ECO100 SIT315 ACCT3610 COMP3600 STK2100 FIT2004 COMP30020 ACTL1101 Stat 101B BANA 200 COSC2473 ENGG1400 AI COMP90043 MMF 1914H PHYS 127 CS584 CIVL2010 ECMT2150 CS 333 CP1406 KIT308 Economics 701 ECON3740 ECE 5759 BFC3340 FINC2012 COMP4500 MATH3871 FIT3080 18-819C Economic ECO202Y5Y PHY100 FINC-780 Econ 100B EC602 IE582 EE450 COMP9517 WRDS 150B ECON 570 LECTURE 2 ECA5101 ECE 4420 ADAD9311 FIT3031 CS 544 MF 703 CS 6140 KIT501 ENGSCI 344 CSC171 IE 332 FINM8007 21S2 COSC 1114 FE545 E471 SIT102 CSC108 MAT301 IAE 101 COP3503 STAT2004 EC 303 CS1026 STAT1203 MATH3171 ISOM5160 IFN657 FIT2014 ACCT2102 DSCI550 STATS 330 ELEC421 COMP3670 QBUS6840 MEES:698B MAST30027 MIET1077 Economics IFT 6758 FIT5122 BUSN5101 CptS 111 HRMT5502 Math2018 PP 312 INFS3200 CZ3005 CSSE1001 SENG 2011 MKTG 553Q BUFN 640 COMP507 ETF5952 DATA 311 ECE4043 BANK3011 finance M3H623544 HW1 INFS 7410 AI6103 STAT3888 INFS3208 ACCT7103 ECOS3013 PSYCH 20B F79MA STAT3006 ENGG952 2X MGSC 7000 ECE4132 MSF 526 MATH 3033 CDS 511 EEEE4120 EEET2465 ECA5103 MATH2070 ELEC3104 BU51019 EEE8147 ENGR20003 COSC 1107 ETF3200 FNCE 435 MSFI 435 ISyE6420 GENG4405 HW ETC5523 IE 7315 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FN1024 MATH0094 MANG 6554 ECOS3003 ELEC6252 C2511C PHY328 EC1060 ECON32202 COMP4002-E1 MATH3063 EFIMM0124 QBUS2310 ECON4411 FUNDAMENTALS ACCT20001 18YX RPM COMP 2711 QBUS6600 BUSS5221 ST3189 FIT1047 MAT344 EGB375 MATH60013 MATH96011 COMP3557 MAST20029 ECM159 EAE1011 ENSCEN 105 SECTION A STA 141C SOSE 2022 PAM006 COMP0048 M40007 ISOM2500 CMPE 142 A06472 MCC150 ACST 8083 GEOG6087 ECON920 FINM7008 ENVENG 4110 COMPSCI 361 ENGRCEE 21 PHYS 1112 ACF2100 ECMM108 COMPS267F MAT00050M MAST30025 CSIT970 MSCI 224 INT202 PUBL0054 MSDM5004 BMAN 21020 BMAN21020 MGMT1002 MATH11150 LAWS7023 ACTL30002 CIVL3340 MATH1002 ECON 8069 COMPSCI 351 IBUS7302 STAT4528 CHEM1101 STAT3925 BUSN 7008 Comp 3120 ECOS2040 SWEN90010 ENGN6528 ECM158 ECON20022 COMP6452 Calculation CITS1401 S1889112 BUS 351 ACTL30008 FIT2091 ECON6002 IBUS6020 PHI 001 ECON30290 MATH7501 ECON10004 MFIN7017 ISYS90043 LAWS7012 ECON30025 COMP30023 COMM1190 ECOM20001 GSBS6009 STAT 337 EMET8002 ECOM90001 ECOM30001 FINC 2012 BUSINESS ENGCV512 ECO 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