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MIPS R4000 Microprocessor User's Manual 43
The CPU Pipeline
3
This chapter describes the basic operation of the CPU pipeline, which
includes descriptions of the delay instructions (instructions that follow a
branch or load instruction in the pipeline), interruptions to the pipeline
flow caused by interlocks and exceptions, and R4400 implementation of an
uncached store buffer.
The FPU pipeline is described in Chapter 6.
Chapter 3
44 MIPS R4000 Microprocessor User's Manual
3.1 CPU Pipeline Operation
The CPU has an eight-stage instruction pipeline; each stage takes one
PCycle (one cycle of PClock, which runs at twice the frequency of
MasterClock). Thus, the execution of each instruction takes at least eight
PCycles (four MasterClock cycles). An instruction can take longer—for
example, if the required data is not in the cache, the data must be retrieved
from main memory.
Once the pipeline has been filled, eight instructions are executed
simultaneously. Figure 3-1 shows the eight stages of the instruction
pipeline; the next section describes the pipeline stages.
Figure 3-1 Instruction Pipeline Stages
PCycle (8-Deep)
Current
CPU
Cycle
IF IS RF EX DF DS TC WB
IF IS RF EX DF DS TC WB
IF IS RF EX DF DS TC WB
IF IS RF EX DF DS TC WB
IF IS RF EX DF DS TC WB
IF IS RF EX DF DS TC WB
IF IS RF EX DF DS TC WB
IF IS RF EX DF DS TC WB
MasterClock
Cycle
MIPS R4000 Microprocessor User's Manual 45
The CPU Pipeline
3.2 CPU Pipeline Stages
This section describes each of the eight pipeline stages:
• IF - Instruction Fetch, First Half
• IS - Instruction Fetch, Second Half
• RF - Register Fetch
• EX - Execution
• DF - Data Fetch, First Half
• DS - Data Fetch, Second Half
• TC - Tag Check
• WB - Write Back
IF - Instruction Fetch, First Half
During the IF stage, the following occurs:
• Branch logic selects an instruction address and the instruction
cache fetch begins.