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EE524/CPTS561 Final exam
创建日期：2024-04-01 17:08:28
标签： EE524
Final exam
EE524/CPTS561 Final exam

• Please show your work, justify the claims you make and point to a source if you are using any.
You may lose points if you use a resource without appropriate references.
• Please DO NOT collaborate on your answers. You should work on the exam questions by
yourself.
• DO NOT post the questions to any forum online
Please type or hand-write your answers and upload them to Blackboard. Please convert your files or
images to PDF format and upload the PDF. It makes annotations and returning feedback to you
much easier.
Submit your exams by 8:00 am on Tuesday, 15 December 2020. Late submissions will be
penalized at 10 points/hour for each hour of delay.
Name: EE524/CPTS561, Fall 2020
Question 1 [8/8/9 points]
(a) For each of the following sequence of branches, assume that you are using a correlating branch
predictor. What is the minimum length of global history required in each case for accurate predictions
for the last branch? As usual, assume that if a branch is taken, it means that the code inside if
condition is not executed. Assume that val is randomly chosen. Explain your reasoning for the
answers.
1. i f ( va l % 12 == 0) { /∗ B1 ∗/
sum += val ; /∗ Not taken path f o r B1 ∗/
}
i f ( va l % 4 == 0) { /∗ B2 ∗/
sum += val ; /∗ Not taken path f o r B2 ∗/
}
i f ( va l % 3 == 0) { /∗ B3 ∗/
sum += val ; /∗ Not taken path f o r B3 ∗/
}
2
Name: EE524/CPTS561, Fall 2020
2. i f ( va l % 2 == 0) { /∗ B1 ∗/
sum += val ; /∗ Not taken path f o r B1 ∗/
}
i f ( va l % 5 == 0) { /∗ B2 ∗/
sum += val ; /∗ Not taken path f o r B2 ∗/
}
i f ( va l % 4 == 0) { /∗ B3 ∗/
sum += val ; /∗ Not taken path f o r B3 ∗/
}
i f ( va l % 20 == 0) { /∗ B4 ∗/
sum += val ; /∗ Not taken path f o r B4 ∗/
}
3
Name: EE524/CPTS561, Fall 2020
(b) Consider the following branches. Assume that if a branch is taken, it means that the code inside
if condition is not executed.
i f ( va l > 5) { /∗ B1 ∗/
/∗ Not taken path f o r B1 ∗/
}
i f ( va l > 3) { /∗ B2 ∗/
/∗ Not taken path f o r B2 ∗/
}
i f ( va l > 2) { /∗ B3 ∗/
/∗ Not taken path f o r B3 ∗/
}
i f ( va l < 0) { /∗ B4 ∗/
/∗ Not taken path f o r B4 ∗/
}
We are using a two-level branch predictor with following properties:
• One bit global history
• One bit local history
Now, we know that the whole branch address is not used to index into the local history table.
As a result of this, B2 and B4 map to the same entry in the local history table. That is, the branch
predictor suffers from aliasing. You have to determine if the branch predictor suffers from destructive
aliasing under any conditions. Please state your reasoning. You may ignore any other branches that
are present in the program.
4
Name: EE524/CPTS561, Fall 2020
5
Name: EE524/CPTS561, Fall 2020
Question 2 [5/6/5/9 points]
(a) Consider a 4 way set associative cache with a total size of 256 KB. Assume that the cache is
virtually indexed and physically tagged. Assuming a 32-bit address and 64-byte blocks, complete
the following table. You can use the next page to show your work.
Table 1: Cache parameters
Parameter Value
Tag bits
Block offset bits
Cache index bits
No. of sets
We will use these cache parameters for the rest of this question.
6
Name: EE524/CPTS561, Fall 2020
(b) For this part, assume that the page size is 128 KB for the machine on which the cache is
implemented. The cache parameters remain the same as in Table 1. If the cache is physically-tagged
and virtually-indexed, does the way-predicting cache suffer from aliasing? Why or why not? Explain
your answer.
(c) What is the minimum page size for which the cache does not suffer from aliasing? Explain your
answer.
7
Name: EE524/CPTS561, Fall 2020
(d) For each of the following addresses, give the cache tag, cache index and set number.
1. 0x80864580
2. 0x1f4dcdde
3. 3c71bb71
8
Name: EE524/CPTS561, Fall 2020
Question 3 [8/9/8 points]
The single thread performance of processor generally increases with the area of the processor.
Consider that in the technology node available to us, the single-thread performance of a core
increases with the square root of the area. For example, if you increase the area of a core by four
times, the performance doubles. You are analyzing the performance of three processors (P1, P2, and
P3) that have different area for a single core as follows:
P1: Single core area = A
P2: Single core area = 4A
P3: Single core area = 16A
(a) You are now analyzing a workload that as a serial portion S, and infinitely parallelizable
portion 1− S. You execute the workload on a system that has 8 processor P1s, and observe a
speedup of 5 over the performance on just a single processor P1. What is the value of S for
the workload?
9
Name: EE524/CPTS561, Fall 2020
(b) Now assume that you have an area budget of 32A. You can utilize this area to include multiple
cores of the same type, e.g. 8 cores of P2 or 2 cores of P3. Which of the three processors
will give the maximum speedup in this case? What is the speedup with respect to a single
processor P1? The workload is same as that of part (a), i.e. the serial portion is S.
(c) Finally, you build a heterogeneous system that has one processor P3 and 16 processor P1s
(total area is 32A). Now the serial portion is of the workload is running on P3 while the parallel
portion is running on the 16 smaller cores (P1). What is the speedup of the heterogeneous
system with respect to a single core P1?
10
Name: EE524/CPTS561, Fall 2020
Question 4 (Short answer questions) [5 points each]
(a) Consider the following two cache replacement and insertion policies in a set associative cache:
• Policy 1: Evict the line at the least recently used position and insert the new line at the
most recently used position.
• Policy 2: Evict the line at the least recently used position and insert the new line at the
least recently used position.
Under what conditions does policy 2 perform better (lower miss rates and hence execution
time) than policy 1?
(b) What are the key differences between shared memory and message passing parallel programming
models?
11
Name: EE524/CPTS561, Fall 2020
(c) Describe the reasons why memory consistency is important in processors. What are the
sufficient conditions to achieve sequential consistency in memory operations?
(d) What are the steps needed to enable trace scheduling in VLIW processors? How can the
processor recover when the trace generated ends up being incorrect?
12
Name: EE524/CPTS561, Fall 2020
(e) One of the design guidelines for domain specific architectures is to invest resources into more
arithmetic units or bigger memories. What are the reasons behind having this design guideline?
13
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MOEC0021 STA 106 ENGG 1300A ENGG 1300 OLET1139 STAT 3503 STAT 206 FEM11149 ELEN 4720 COMP20003 SOLA1070 CS574 C11CS LINB29H3 MAST90083 ECON7200 STAT 610 LINB29 DSM-5 COMP3161 EEEN40010 MATH 4431 K353 STA 3386 IERG4300 COMS W4167 ENG5298 AMME 2302 CS3910 COMPSCI 320 STATS 369 GR5242 COSC 328 CSCI435 MGTS1301 INFS2200 COMP3900 CIS 375 Module AE03 COMP3121 CS260 HAM503 MGMT5050 INT3075 COSC 285 GEOL0029 GEGE2X01 STAT1201 MATH1061 MMF1941H STAT 5060 CS 520 COMP 4320 MSIN0104 000T FINS3648 ECMT2160 ECON4003 Phys 129L CSE 142 CS 3130 MGEB01 EECS 340 Finance (20443/20444) ECMM149 COMP5310 EEEN60180 CSC 111 AT2 CSCI 4430 STAB57 MA/CSC 427 MATH322 D100 CSCI544 CITS3004 CI6227 CSE 565 APCO 1P01 852L1 ELEC S411F COMP3207 STATS330 ECON7530 FIT5149 CSI4104 CMPT 371 COMP201 SEHS4696 FI4003 MATH6182 CG1 WS MATH401 MGT 205 QTM 110 COMP 0137 MACE12201 FIT5210 ECE 544 BISM7206 HUDM 6055 ECON3203 STATS 210 MSCI 570 MATH6173 COMPSCI4039 Accounting COM3503 AOE2024 ECON213 PSYC10004 Control Data 100/200A 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